FPGA & VLSI Interview Questions

List of commonly asked questions in the field of VLSI & FPGA. List will keep extending in future.
You guys are welcome to share questions related to VLSI/FPGA/ASIC, put them in comments section, I will ad them also in the list below:

1. What's the difference between latch and flip flop?
2. Make a 2 input AND/OR/XOR gate using 2:1 MUX.
3. Make a D-latch using 2:1 MUX.
4. Explain any FPGA architecture.
5. What is global clock buffer and why it is used?
6. How many 2:1 MUXes will be needed to create a 4096:1 MUX?
7. What are hold time and setup time in context of flip flop? Also explain metastablity in flip flops.
8. Explain FPGA design flow.
9. What is netlist simulation and how to perform this?
10. How many 4x4 multipliers are needed (in addition to full adders) to realize 8x8 multiplier?
11. Draw state machine diagram for a logic to detect binary sequence "101011".
12. What is pipelining in digital circuit and how does it improve the timing performance? Also explain it's side effects.
13. What's register replication, why do we need register replication in digital circuits?
14. What's metastability and how we can reduce it's probability? Explain two flip flop synchronizer.
15.  What's EDIF file in context of FPGA synthesis?
16. Calculate the depth of FIFO required if write clock is 50MHz, read clock is 20MHz and block size is 100.
17. How to write verilog code for following RAM configuration modes:
• Single port/dual port write first mode
• Single port/dual port read first mode
18. Draw 2:1 MUX using transmission gates.
19. Implement Y = AB + BC function using 4:1 MUX.
20. What's the difference between blocking and non-blocking assignments in Verilog?
21.  Design an FSM that can generate a single pulse after certain no. of rising clk edge. Such no. is defined by the input.
22.  How to fix the hold-time violation after the chip was fabricated?
23.  How is race avoided in SystemVerilog testbench?
24.  How many flops will be there in FSM if you have 4 states?
25.  When clock is x, what is the output?
26.  How would you design for clock domain crossing?
27.  Using a simple logic gate, convert a SET type flop to a RESET type flop.
28.  What is multi-cycle and false path in a design?
29.  What is skew in a design?
30.  What is the difference between tasks and function in sytem verilog. Which one of them is reentrant?
31. What is the difference between block RAM & Distributed RAM in an FPGA?
32. How will you move enable control to the data path of a D-flop?
33. How will you move sync set/rst logic to data path of a D-flop?